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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11145554 B1

PDFFull Text
Date of Patent:
Oct. 12, 2021

Filed:

Nov. 19, 2019

Method for source/drain contact formation in semiconductor devices

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shao-Ming Koh, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

I-Wen Wu, Hsinchu, TW;

Fu-Kai Yang, Hsinchu, TW;

Jia-Heng Wang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Jami Valentine Miller

Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 27/06 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/167 (2006.01); H01L 29/45 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823871 (2013.01); H01L 21/02063 (2013.01); H01L 21/324 (2013.01); H01L 21/76805 (2013.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01); H01L 21/76889 (2013.01); H01L 21/76895 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 23/535 (2013.01); H01L 27/0605 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/7845 (2013.01); H01L 29/7848 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/823807 (2013.01); H01L 29/165 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01); H01L 29/7843 (2013.01);
Abstract

A semiconductor device includes an n-type FET device and a p-type FET device. The n-type FET device includes a first substrate region, a first gate stack, a first gate spacer over sidewalls of the first gate stack, and an n-type epitaxial feature in a source/drain (S/D) region of the n-type FET device. The p-type FET device includes a second substrate region, a second gate stack, a second gate spacer over sidewalls of the second gate stack, and a p-type epitaxial feature in an S/D region of the p-type FET device. A vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the p-type epitaxial feature.

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