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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11139400 B1

PDFFull Text
Date of Patent:
Oct. 05, 2021

Filed:

Feb. 10, 2020

Non-planar semiconductor device having hybrid geometry-based active region

Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Seiyon Kim, Portland, OR (US);

Rafael Rios, Austin, TX (US);

Fahmida Ferdousi, Hillsboro, OR (US);

Kelin J. Kuhn, Aloha, OR (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:

Lerner, David, Littenberg, Krumholz & Mentlik, LLP

Primary Examiner:

Changhyun Yi

Int. Cl.
CPC ...
H01L 29/78 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/10 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7853 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 29/0673 (2013.01); H01L 29/0684 (2013.01); H01L 29/1037 (2013.01); H01L 29/1054 (2013.01); H01L 29/16 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01);
Abstract

Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

Find Patent Forward Citations

Quick Actions:

Kim, Seiyon. (2021). Non-planar semiconductor device having hybrid geometry-based active region (U.S. Patent No. 11139400). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11139400

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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