The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Mar. 27, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Seiji Takahashi, Hsinchu, TW;

Chen-Jong Wang, Hsin-Chu, TW;

Dun-Nian Yaung, Taipei, TW;

Jung-I Lin, Hsinchu, TW;

Jhy-Jyi Sze, Hsin-Chu, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Yimin Huang, Hsinchu, TW;

King Liao, Tainan, TW;

Shen-Hui Hong, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 28/75 (2013.01); H01L 21/76834 (2013.01); H01L 21/76849 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure disposed over a substrate. A plurality of conductive interconnect layers are disposed within the dielectric structure. The plurality of conductive interconnect layers include alternating layers of interconnect wires and interconnect vias. A metal-insulating-metal (MIM) capacitor is arranged within the dielectric structure. The MIM capacitor has a lower conductive electrode separated from an upper conductive electrode by a capacitor dielectric structure. The MIM capacitor vertically extends past two or more of the plurality of conductive interconnect layers.


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