The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11133291 B1

Date of Patent:

Sep. 28, 2021

Filed:

Mar. 13, 2020

Chip package structure with multi-chip stack

Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Chih-Yen Su, Hsinchu County, TW;

Chun-Te Lin, Hsinchu County, TW;

Assignee:

POWERTECH TECHNOLOGY INC., Hsinchu County, TW;

Attorney:

Winston Hsu

Primary Examiner:

Mamadou L Diallo

Int. Cl.

CPC ...

H01L 25/065 (2006.01); H01L 23/12 (2006.01); H01L 23/538 (2006.01);

U.S. Cl.

CPC ...

H01L 25/0657 (2013.01); H01L 23/12 (2013.01); H01L 23/5384 (2013.01);

Abstract

A chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.

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Su, Chih-Yen. (2021). Chip package structure with multi-chip stack (U.S. Patent No. 11133291). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11133291

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