The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

May. 06, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chung-Chiang Wu, Taichung, TW;

Chia-Ching Lee, New Taipei, TW;

Da-Yuan Lee, Jhubei, TW;

Hsueh Wen Tsau, Zhunan Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 29/51 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/28026 (2013.01); H01L 21/28088 (2013.01); H01L 21/823842 (2013.01); H01L 29/4966 (2013.01); H01L 29/66636 (2013.01); H01L 29/7834 (2013.01); H01L 29/165 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/7848 (2013.01);
Abstract

Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.


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