The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Jun. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Georg Seidemann, Landshut, DE;

Bernd Waidhas, Pettendorf, DE;

Thomas Wagner, Regelsbach, DE;

Andreas Wolter, Regensburg, DE;

Andreas Augustin, Munich, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/00 (2006.01); H01L 49/02 (2006.01); H01F 17/04 (2006.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 28/10 (2013.01); H01F 17/04 (2013.01); H01L 21/02447 (2013.01); H01L 21/565 (2013.01); H01L 23/645 (2013.01); H01L 24/13 (2013.01);
Abstract

The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.


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