The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Jul. 15, 2019
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Chi-Tsung Chiu, Kaohsiung, TW;

Hui-Ying Hsieh, Kaohsiung, TW;

Hui Hua Lee, Kaohsiung, TW;

Cheng Yuan Chen, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/13 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 21/561 (2013.01); H01L 23/13 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 24/19 (2013.01); H01L 24/97 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73151 (2013.01);
Abstract

A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.


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