The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2021
Filed:
Dec. 11, 2019
Infineon Technologies Ag, Neubiberg, DE;
Johann Gatterbauer, Parsberg, DE;
Katrin Albers, Regensburg, DE;
Joerg Busch, Regensburg, DE;
Klaus Goller, Regensburg, DE;
Norbert Mais, Munich, DE;
Marianne Kolitsch, Villach, AT;
Michael Nelhiebel, Villach, AT;
Rainer Pelzer, Wernberg, AT;
Bernhard Weidgans, Bernhardswald, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.