The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Jun. 05, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chih-Liang Chen, Hsinchu, TW;

Lei-Chun Chou, Taipei, TW;

Jack Liu, Taipei, TW;

Kam-Tou Sio, Hsinchu County, TW;

Hui-Ting Yang, Hsinchu County, TW;

Wei-Cheng Lin, Taichung, TW;

Chun-Hung Liou, Hsinchu, TW;

Jiann-Tyng Tzeng, Hsinchu, TW;

Chew-Yuen Young, Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/82 (2006.01); H01L 23/52 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/48 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/76871 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/41791 (2013.01);
Abstract

A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.


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