The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Oct. 15, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Deyan Chen, Shanghai, CN;

Mao Li, Shanghai, CN;

Leong Tee Koh, Shanghai, CN;

Dae-Sub Jung, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 29/402 (2013.01); H01L 29/66681 (2013.01);
Abstract

The present disclosure provides an LDMOS device and a manufacturing method thereof. The LDMOS device includes: a substrate, a drift region formed in the substrate; a gate structure, located on the substrate on one side of the drift region, and covering part of the drift region; a drain region, located in the drift region on one side of the gate structure, an isolation structure located on the substrate, the isolation structure located between the drain region and the gate structure; a gate electrode, located on the gate structure and electrically connected with the gate structure; a drain electrode, located on the drain region and electrically connected with the drain region; a block layer, covering the drift region and the isolation structure between the gate electrode and the drain electrode in a shape-preserving manner; and a groove electrode located on the block layer, the groove electrode located between the isolation structure and the gate structure, and at least covering part of the top of the isolation structure. The LDMOS device improves a device breakdown voltage, and cannot increase Rdson.


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