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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11121142 B1

PDFFull Text
Date of Patent:
Sep. 14, 2021

Filed:

Dec. 31, 2019

Memory structure and manufacturing method therefor

Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Che-Jui Hsu, Taichung, TW;

Chun-Sheng Lu, Taichung, TW;

Ying-Fu Tung, Taichung, TW;

Chen-Wei Liao, Taichung, TW;

Assignee:

Winbond Electronics Corp., Taichung, TW;

Attorney:

JCIPRNET

Primary Examiner:

Zandra V Smith

Assistant Examiner:

Andre C Stevenson

Int. Cl.
CPC ...
H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/788 (2006.01); H01L 27/11568 (2017.01); H01L 29/792 (2006.01); H01L 23/522 (2006.01); H01L 21/321 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76877 (2013.01); H01L 27/11568 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01);
Abstract

A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

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