The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Oct. 15, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chieh-Fei Chiu, Tainan, TW;

Wen-Ting Chu, Kaohsiung, TW;

Yong-Shiuan Tsair, Tainan, TW;

Yu-Wen Liao, New Taipei, TW;

Chin-Yu Mei, Hsin-Chu, TW;

Po-Hao Tseng, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 45/124 (2013.01); H01L 23/3114 (2013.01); H01L 23/481 (2013.01); H01L 23/4952 (2013.01); H01L 45/1253 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode.


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