The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

May. 15, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kevin K. Chan, Staten Island, NY (US);

Sivananda K. Kanakasabapathy, Pleasanton, CA (US);

Babar A. Khan, Ossining, NY (US);

Masaharu Kobayashi, Tokyo, JP;

Effendi Leobandung, Stormville, NY (US);

Theodoras E. Standaert, Clifton Park, NY (US);

Xinhui Wang, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 29/94 (2006.01); H01L 27/12 (2006.01); G06F 30/30 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/10 (2020.01); H01L 49/02 (2006.01); H01L 29/04 (2006.01); H01L 27/07 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10832 (2013.01); G06F 30/10 (2020.01); G06F 30/30 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 27/0733 (2013.01); H01L 27/10826 (2013.01); H01L 27/10829 (2013.01); H01L 27/10858 (2013.01); H01L 27/10867 (2013.01); H01L 27/10879 (2013.01); H01L 27/1203 (2013.01); H01L 27/1211 (2013.01); H01L 28/40 (2013.01); H01L 29/04 (2013.01); H01L 29/0649 (2013.01); H01L 29/517 (2013.01); H01L 29/66181 (2013.01); H01L 29/945 (2013.01); H01L 27/0629 (2013.01);
Abstract

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.


Find Patent Forward Citations

Loading…