The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2021
Filed:
Jun. 07, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Lilia May, Chandler, AZ (US);
Robert Alan May, Chandler, AZ (US);
Amruthavalli Pallavi Alur, Tempe, AZ (US);
Robert L. Sankman, Phoenix, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H05K 1/02 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 23/5226 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H05K 1/0243 (2013.01); H01L 2223/6627 (2013.01);
Abstract
An integrated-circuit package substrate includes a pseudo-stripline that is shielded below a lower solder-resist layer and an upper solder-resist layer, where an upper shielding plane is sandwiched between the lower and upper solder-resist layers. The lower solder-resist layer can at least partially overlap a landing-pad region of a landing-pad via that penetrates a top build-up layer which is contacted by the lower solder-resist layer.