The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2021
Filed:
May. 21, 2019
Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Anderson Lin, Hsinchu, TW;
Chun-Ren Cheng, Hsin-Chu, TW;
Chi-Yuan Shih, Hsinchu, TW;
Shih-Fen Huang, Jhubei, TW;
Yi-Chuan Teng, Zhubei, TW;
Yi Heng Tsai, Hsinchu, TW;
You-Ru Lin, New Taipei, TW;
Yen-Wen Chen, Hsinchu County, TW;
Fu-Chun Huang, Zhubei, TW;
Fan Hu, Taipei, TW;
Ching-Hui Lin, Taichung, TW;
Yan-Jie Liao, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.