The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Aug. 03, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Gulbagh Singh, Uttar Pradesh, IN;

Cheng-Yeh Huang, Tainan, TW;

Chin-Nan Chang, Tainan, TW;

Chih-Ming Lee, Tainan, TW;

Chi-Yen Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/324 (2006.01); H01L 29/45 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 21/76202 (2013.01); H01L 21/76224 (2013.01); H01L 21/76895 (2013.01); H01L 29/456 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.


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