logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11094824 B1

PDFFull Text
Date of Patent:
Aug. 17, 2021

Filed:

Nov. 15, 2019

Forming a sacrificial liner for dual channel devices

Applicant:

Tessera, Inc., San Jose, CA (US);

Inventors:

Huiming Bu, Glenmont, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Dechao Guo, Niskayuna, NY (US);

Sivananda K Kanakasabapathy, Pleasanton, CA (US);

Peng Xu, Santa Clara, CA (US);

Assignee:

Tessera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:

Cuong B Nguyen

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 21/3065 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/3065 (2013.01); H01L 21/324 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/1037 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion.

Find Patent Forward Citations

Loading…