The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2021
Filed:
Aug. 21, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Kam-Tou Sio, Zhubei, TW;
Chih-Ming Lai, Hsinchu, TW;
Chun-Kuang Chen, Guanxi Township, TW;
Chih-Liang Chen, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Chi-Yeh Yu, Hsinchu, TW;
Jiann-Tyng Tzeng, Hsin Chu, TW;
Ru-Gun Liu, Zhubei, TW;
Wen-Hao Chen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.