The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2021
Filed:
May. 07, 2019
Method of generating layout diagram including dummy pattern conversion and system of generating same
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Ritesh Kumar, Hsinchu, TW;
Chung-Hsing Wang, Baoshan Township, TW;
Kuo-Nan Yang, Hsinchu, TW;
Hiranmay Biswas, Kolkata, IN;
Shu-Yi Ying, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.