The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2021
Filed:
Jul. 01, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Kevin L. Baker, Boise, ID (US);
Robert K. Grubbs, Boise, ID (US);
Farrell M. Good, Meridian, ID (US);
Ervin T. Hill, Boise, ID (US);
Bhumika Chhabra, Boise, ID (US);
Jay S. Brown, Boise, ID (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1233 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/144 (2013.01); H01L 45/1683 (2013.01);
Abstract
An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.