The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Jan. 30, 2018
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Alexander Reznicek, Troy, NY (US);

Shogo Mochizuki, Clifton Park, NY (US);

Veeraraghavan S. Basker, Schenectady, NY (US);

Nicolas L. Breil, Beacon, NY (US);

Oleg Gluschenkov, Tannersville, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/165 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.


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