The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Jan. 15, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Chiang Chen, Hsinchu, TW;

Chun-Ting Wu, Kaohsiung, TW;

Ching-Hou Su, Hsinchu, TW;

Chih-Pin Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76832 (2013.01); H01L 21/02274 (2013.01); H01L 21/76834 (2013.01); H01L 23/5226 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13024 (2013.01);
Abstract

A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.


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