The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Nov. 06, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-Yu Yang, Changhua County, TW;

Chia-Ta Yu, Hsinchu, TW;

Kai-Hsuan Lee, Hsinchu, TW;

Sai-Hooi Yeong, Hsinchu County, TW;

Feng-Cheng Yang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A method includes providing a device structure having a substrate, an isolation structure over the substrate, and two fins extending from the substrate and through the isolation structure, each fin having two source/drain (S/D) regions and a channel region; depositing a first dielectric layer over top and sidewall surfaces of the fins and over the isolation structure; forming a gate stack over the first dielectric layer and engaging each fin at the respective channel region; treating surfaces of the gate stack and the first dielectric layer such that the surfaces of the gate stack are more attachable to a second dielectric layer than the surfaces of the first dielectric layer are; after the treating of the surfaces, depositing the second dielectric layer; and etching the first dielectric layer to expose the S/D regions of the fins.


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