Enhanced read sensing margin and minimized vdd for sram cell arrays

Abstract

A structure for an integrated circuit is disclosed for storing data. The integrated circuit includes a memory cell array of bit cells configured in a static random access memory (SRAM) architecture. The memory cell array is coupled to wordlines arranged in rows that control operations such as Read and Write operations. To enhance the read sensing margin of the SRAM configuration, the read port of a bit cell may include a wordline that drives two transistors (e.g., a PMOS and an NMOS transistor) to reduce data-dependent current leakage from a read bitline. An additional weak transistor keeper configuration may be used in the integrated circuit to compensate for current leakage from the read bitline. For example, a weak NMOS keeper that includes a sense amplifier, an inverter, and an NMOS connected to supply voltage VDD provides a path between the read bitline and VDD through the weak NMOS keeper.