The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Dec. 12, 2019
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Jung-Che Chang, Tainan, TW;

Bao-Tzeng Huang, Pingtung County, TW;

Yu-Hong Huang, Tainan, TW;

Siou-Cyun Lin, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76813 (2013.01); H01L 21/7681 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 28/20 (2013.01); H01L 28/60 (2013.01);
Abstract

A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.


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