The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Oct. 07, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-Yen Yu, New Taipei, TW;

Che-Cheng Chang, New Taipei, TW;

Tung-Wen Cheng, New Taipei, TW;

Zhe-Hao Zhang, Hsinchu, TW;

Bo-Feng Young, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 21/02 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/267 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/0262 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/165 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/267 (2013.01);
Abstract

A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.


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