The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Aug. 28, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsin-Che Chiang, Taipei, TW;

Ju-Yuan Tzeng, New Taipei, TW;

Chun-Sheng Liang, Changhua County, TW;

Chih-Yang Yeh, Hsinchu County, TW;

Shu-Hui Wang, Hsinchu, TW;

Jeng-Ya David Yeh, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 29/165 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42372 (2013.01); H01L 21/28088 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/165 (2013.01); H01L 29/517 (2013.01); H01L 29/7843 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.


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