The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2021
Filed:
Sep. 22, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Hui-Ting Yang, Zhubei, TW;
Chih-Ming Lai, Hsinchu, TW;
Chun-Kuang Chen, Guanxi Township, TW;
Chih-Liang Chen, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Jiann-Tyng Tzeng, Hsin Chu, TW;
Kam-Tou Sio, Zhubei, TW;
Meng-Hung Shen, Zhudong Township, TW;
Ru-Gun Liu, Zhubei, TW;
Wei-Cheng Lin, Taichung, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.