The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Jan. 10, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shao-Ming Koh, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

Fu-Kai Yang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 21/4757 (2006.01); H01L 21/302 (2006.01); H01L 21/285 (2006.01); H01L 23/485 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/3065 (2006.01); H01L 21/8238 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/02057 (2013.01); H01L 21/28525 (2013.01); H01L 21/302 (2013.01); H01L 21/3065 (2013.01); H01L 21/30608 (2013.01); H01L 21/31138 (2013.01); H01L 21/47573 (2013.01); H01L 21/76801 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 23/485 (2013.01); H01L 27/0924 (2013.01); H01L 29/7848 (2013.01); H01L 29/165 (2013.01); H01L 29/41791 (2013.01); H01L 29/665 (2013.01);
Abstract

Semiconductor devices and methods of forming the same are provided. In one embodiments, the method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure, a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features. The method further includes etching the one or more dielectric layers to form openings exposing the first and second S/D features, forming a masking layer over the first S/D feature, implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, removing the masking layer; and etching the first and second S/D features with an oxygen-atom-containing etchant.


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