The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2021
Filed:
Oct. 14, 2019
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Tsung-Yao Wen, Hsinchu, TW;
Angus Hsiao, Changhua County, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/8258 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0338 (2013.01); H01L 21/3086 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/8258 (2013.01);
Abstract
A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a hard mask (HM) layer over the dielectric layer, forming a fin trench through the HM layer and the dielectric layer and extending down to the substrate, forming a semiconductor feature in the fin trench and removing the HM layer to expose an upper portion of the semiconductor feature to form fin features.