The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Nov. 30, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Hsien Huang, Hsinchu, TW;

Hong-Chen Cheng, Hsinchu, TW;

Cheng Hung Lee, Hsinchu, TW;

Hung-Jen Liao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); H01L 23/522 (2006.01); G11C 7/18 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1128 (2013.01); G11C 7/18 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/0688 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.


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