The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2021
Filed:
Feb. 04, 2020
Silicon Storage Technology, Inc., San Jose, CA (US);
Jinho Kim, Saratoga, CA (US);
Elizabeth Cuevas, Los Gatos, CA (US);
Parviz Ghazavi, San Jose, CA (US);
Bernard Bertello, Bouches du Rhones, FR;
Gilles Festes, Fuveau, FR;
Catherine Decobert, Pourrieres, FR;
Yuri Tkachev, Sunnyvale, CA (US);
Bruno Villard, Aix en Provence, FR;
Nhan Do, Saratoga, CA (US);
Silicon Storage Technology, Inc., San Jose, CA (US);
Abstract
A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge. An oxide layer is formed having first and second portions extending along the logic and memory cell regions of the substrate surface, respectively, and a third portion extending along the floating gate edge. A non-conformal layer is formed having a first, second and third portions covering the oxide layer first, second and third portions, respectively. An etch removes the non-conformal layer third portion, and thins but does not entirely remove the non-conformal layer first and second portions. An etch reduces the thickness of the oxide layer third portion. After removing the non-conformal layer first and second portions, a control gate is formed on the oxide layer second portion and a logic gate is formed on the oxide layer first portion.