The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Dec. 02, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kuo-Chi Tu, Hsinchu, TW;

Chu-Jie Huang, Tainan, TW;

Sheng-Hung Shih, Hsinchu, TW;

Nai-Chao Su, Tainan, TW;

Wen-Ting Chu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 13/00 (2006.01); H01L 21/02 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0007 (2013.01); H01L 21/02008 (2013.01); H01L 21/3212 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01);
Abstract

A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.


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