The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Nov. 14, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Tai-I Yang, Hsinchu, TW;

Chun-Yi Yang, Hsinchu, TW;

Chih-Hao Lin, Hsinchu, TW;

Hong-Seng Shue, Zhubei, TW;

Ruei-Hung Jang, Jhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 23/525 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5256 (2013.01); H01L 23/5258 (2013.01); H01L 23/62 (2013.01); H01L 24/05 (2013.01); H01L 24/45 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05571 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/00014 (2013.01);
Abstract

The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.


Find Patent Forward Citations

Loading…