The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Dec. 02, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kuo-Chi Tu, Hsinchu, TW;

Chu-Jie Huang, Tainan, TW;

Sheng-Hung Shih, Hsinchu, TW;

Nai-Chao Su, Tainan, TW;

Wen-Ting Chu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 13/00 (2006.01); H01L 21/02 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0007 (2013.01); H01L 21/02008 (2013.01); H01L 21/3212 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01);
Abstract

A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.


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