The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2021
Filed:
Jun. 17, 2019
Applied Materials, Inc., Santa Clara, CA (US);
Gaurav Thareja, Santa Clara, CA (US);
Keyvan Kashefizadeh, Dublin, CA (US);
Xikun Wang, Sunnyvale, CA (US);
Anchuan Wang, San Jose, CA (US);
Sanjay Natarajan, Portland, OR (US);
Sean M. Seutter, Munich, DE;
Dong Wu, Fremont, CA (US);
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Abstract
A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.