The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

Dec. 24, 2018
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Lin Hu, Malta, NY (US);

Veeraraghavan S. Basker, Schenectady, NY (US);

Brian J. Greene, Wappingers Falls, NY (US);

Kai Zhao, Hopewell Junction, NY (US);

Daniel Jaeger, Saratoga Springs, NY (US);

Keith Tabakman, Wilton, NY (US);

Christopher Nassar, Malta, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0653 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 29/41791 (2013.01); H01L 29/6681 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.


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