The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2021
Filed:
Dec. 31, 2017
Intel Corporation, Santa Clara, CA (US);
Sanjeev Jahagirdar, Folsom, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Yoav Harel, Carmichael, CA (US);
Kenneth Brand, El Dorado Hills, CA (US);
Chandra Gurram, Folsom, CA (US);
Eric Finley, Ione, CA (US);
Bhushan Borole, Rancho Cordova, CA (US);
Carlos Nava Rodriguez, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.