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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10980127 B1

PDFFull Text
Date of Patent:
Apr. 13, 2021

Filed:

Jun. 07, 2019

Methods for fabricating printed circuit board assemblies with high density via array

Applicant:

Ttm Technologies, Inc., St. Louis, MO (US);

Inventors:

Michael Len, Skaneateles, NY (US);

Chong Mei, Jamesville, NY (US);

Michael Lugert, Manlius, NY (US);

Raj Kumar, Anaheim, CA (US);

Assignee:

TTM Technologies Inc., Santa Ana, CA (US);

Attorney:

Polsinelli PC

Primary Examiner:

Xiaoliang Chen

Int. Cl.
CPC ...
H05K 1/00 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 1/16 (2006.01); H05K 3/46 (2006.01); H01L 21/44 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/34 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/373 (2006.01); H01L 23/473 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H05K 3/00 (2006.01); H05K 3/40 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 3/0047 (2013.01); H05K 3/0094 (2013.01); H05K 3/4038 (2013.01); H05K 3/42 (2013.01);
Abstract

A method is provided for forming a printed circuit board (PCB) assembly. The method may include drilling a first plurality of vias having a first diameter in a PCB and filling the first plurality of vias to form a first plurality of plated or filled vias. The method may also include drilling a second plurality of vias having a second diameter in the PCB, and filling the second plurality of vias to form a second plurality of plated or filled vias. The first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias such that the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.

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