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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10978594 B1

PDFFull Text
Date of Patent:
Apr. 13, 2021

Filed:

Dec. 22, 2015

Transistor comprising a channel placed under shear strain and fabrication process

Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Emmanuel Augendre, Montbonnot, FR;

Maxime Argoud, La Chapelle de la Tour, FR;

Sylvain Maitrejean, Grenoble, FR;

Pierre Morin, Albany, NY (US);

Raluca Tiron, Saint-Martin-le-Vinoux, FR;

Assignee:

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris, FR;

Attorney:

BakerHostetler

Primary Examiner:

Cuong Q Nguyen

Assistant Examiner:

Peter M Albrecht

Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 29/1033 (2013.01); H01L 29/1037 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/78 (2013.01); H01L 29/7842 (2013.01); H01L 29/78654 (2013.01);
Abstract

The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.

Find Patent Forward Citations

Augendre, Emmanuel. (2021). Transistor comprising a channel placed under shear strain and fabrication process (U.S. Patent No. 10978594). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10978594

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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