The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2021
Filed:
Feb. 18, 2020
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Wei-Cheng Lin, Taichung, TW;
Chih-Liang Chen, Hsinchu, TW;
Chih-Ming Lai, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Jiann-Tyng Tzeng, Hsinchu, TW;
Kam-Tou Sio, Zhubei, TW;
Ru-Gun Liu, Zhubei, TW;
Shih-Wei Peng, Hsinchu, TW;
Wei-Chen Chien, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.