The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Jan. 10, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Hong-Ru Liu, Chiayi County, TW;

Kuei-Hsuan Yu, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/3065 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); H01L 27/10814 (2013.01); H01L 27/10817 (2013.01); H01L 27/10852 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 27/10891 (2013.01); H01L 21/3065 (2013.01); H01L 29/42376 (2013.01); H01L 29/7827 (2013.01);
Abstract

A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward.


Find Patent Forward Citations

Liu, Hong-Ru. (2021). Memory cell (U.S. Patent No. 10971497). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10971497

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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