The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2021
Filed:
Oct. 11, 2019
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Haohua Zhou, Fremont, CA (US);
Tze-Chiang Huang, Saratoga, CA (US);
Mei Hsu Wong, Saratoga, CA (US);
Abstract
A System On Chip (SOC) current profile model for Integrated Voltage Regulator (IVR) co-design may be provided. A first current profile model may be extracted corresponding to an SOC at a first design stage of the SOC. Then it may be determined that an IVR and the SOC pass a first co-simulation based on the extracted first current profile model. Next, a second current profile model may be extracted corresponding to the SOC at a second design stage of the SOC. Then it may be determined that the IVR and the SOC pass a second co-simulation based on the extracted second current profile model. A third current profile model may be extracted corresponding to the SOC at a third design stage of the SOC. Then it may be determined that the IVR and the SOC pass a third co-simulation based on the extracted third current profile model.