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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10964595 B1

PDFFull Text
Date of Patent:
Mar. 30, 2021

Filed:

Apr. 22, 2019

Method for singulating packaged integrated circuits and resulting structures

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yen-Ping Wang, Hemei Township, TW;

Ming-Kai Liu, Hsinchu, TW;

Kai-Chiang Wu, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

David A Zarneke

Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/308 (2006.01); H01L 21/782 (2006.01); H01L 21/784 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/3086 (2013.01); H01L 21/561 (2013.01); H01L 23/3114 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 21/782 (2013.01); H01L 21/784 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/1191 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/94 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.

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