The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
Sep. 19, 2019
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 23/373 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4871 (2013.01); H01L 21/4878 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/36 (2013.01); H01L 23/3736 (2013.01); H01L 23/3737 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/83101 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3511 (2013.01);
Abstract
A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.