The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Dec. 18, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wen-Chin Chen, Kaohsiung, TW;

Cheng-Yi Wu, Taichung, TW;

Yu-Hung Cheng, Tainan, TW;

Ren-Hua Guo, Taichung, TW;

Hsiang Liu, Hsinchu, TW;

Chin-Szu Lee, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/102 (2006.01); H01L 21/00 (2006.01); H01L 21/20 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2022 (2013.01); H01L 21/02002 (2013.01); H01L 21/0243 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02502 (2013.01); H01L 21/02516 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/02636 (2013.01); H01L 21/02639 (2013.01); H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66287 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01); H01L 21/30608 (2013.01);
Abstract

A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.


Find Patent Forward Citations

Loading…