The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Jun. 07, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Yi-Wei Chen, Taichung, TW;

Hsu-Yang Wang, Tainan, TW;

Chun-Chieh Chiu, Keelung, TW;

Shih-Fang Tzou, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/76 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10888 (2013.01); H01L 21/76804 (2013.01); H01L 21/76805 (2013.01); H01L 21/76814 (2013.01); H01L 21/76819 (2013.01); H01L 21/76895 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01);
Abstract

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.


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