The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Aug. 15, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Rahul Sharangpani, Fremont, CA (US);

Raghuveer S. Makala, Campbell, CA (US);

Seung-Yeul Yang, Pleasanton, CA (US);

Fei Zhou, San Jose, CA (US);

Adarsh Rajashekhar, Santa Clara, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11597 (2017.01); G11C 11/22 (2006.01); H01L 27/11592 (2017.01); H01L 27/1159 (2017.01); H01L 27/11587 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11597 (2013.01); G11C 11/223 (2013.01); H01L 27/1159 (2013.01); H01L 27/11587 (2013.01); H01L 27/11592 (2013.01);
Abstract

A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a respective transition metal nitride liner and a respective conductive fill material layer, a vertical semiconductor channel vertically extending through the alternating stack, a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.


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