The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Sep. 25, 2019
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc China Company, Limited, Shanghai, CN;

Tsmc Nanjing Company, Limited, Nanjing, CN;

Inventors:

XiuLi Yang, Shanghai, CN;

Ching-Wei Wu, Caotun Town, TW;

He-Zhou Wan, Shanghai, CN;

Kuan Cheng, Shanghai, CN;

Luping Kong, Nanjing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/10 (2006.01); G11C 7/22 (2006.01); G11C 8/18 (2006.01); G11C 8/08 (2006.01); G11C 11/419 (2006.01); G11C 7/10 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01); G11C 7/222 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

A circuit includes a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when a select signal has a first logical state, and pass the second address to the output when the select signal has a second logical state different from the first logical state. The circuit also includes a decoder configured to decode the passed first address or second address.


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