The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Aug. 18, 2019
Applicants:

Kla Corporation, Milpitas, CA (US);

Shan Zhu;

Inventors:

Junqing Huang, Fremont, CA (US);

Paul Russell, Brighton, GB;

Hucheng Lee, Cupertino, CA (US);

Kenong Wu, Davis, CA (US);

Assignee:

KLA Corp., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J 37/28 (2006.01); G01N 21/95 (2006.01); H01J 37/244 (2006.01);
U.S. Cl.
CPC ...
H01J 37/28 (2013.01); G01N 21/9501 (2013.01); H01J 37/244 (2013.01); G01N 2223/611 (2013.01);
Abstract

Methods and systems for detecting defects in a logic region on a wafer are provided. One method includes acquiring information for different types of design-based care areas in a logic region of a wafer. The method also includes designating the different types of the design-based care areas as different types of sub-regions and, for a localized area within the logic region, assigning two or more instances of the sub-regions located in the localized area to a super-region. In addition, the method includes generating one scatter plot for all of the two or more instances of the sub-regions assigned to the super-region. The one scatter plot is generated with different segmentation values for the output corresponding to the different types of the sub-regions. The method further includes detecting defects in the sub-regions based on the one scatter plot.


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